{"id":5077,"date":"2014-03-18T10:30:57","date_gmt":"2014-03-18T14:30:57","guid":{"rendered":"http:\/\/blog.nccomputertech.com\/?p=5077"},"modified":"2014-03-18T10:30:57","modified_gmt":"2014-03-18T14:30:57","slug":"understanding-the-pcie-interface-and-how-it-benefits-solid-state-storage","status":"publish","type":"post","link":"https:\/\/nccomputertech.com\/techtalk\/2014\/03\/18\/understanding-the-pcie-interface-and-how-it-benefits-solid-state-storage\/","title":{"rendered":"Understanding the PCIe interface and how it benefits solid state storage"},"content":{"rendered":"<p style=\"text-align:center;\"><a href=\"http:\/\/www.techspot.com\/news\/56014-understanding-the-pcie-interface-and-how-it-benefits-solid-state-storage.html\"><img data-recalc-dims=\"1\" decoding=\"async\" alt=\"\" src=\"https:\/\/i0.wp.com\/nccomputertech.com\/techtalk\/wp-content\/uploads\/2014\/03\/2014-03-17-image-1.jpg\" \/><\/a><\/p>\n<p>Ever since solid state storage was put on the map, we&#8217;ve seen tremendous strides in storage performance across consumer and enterprise computing uses with the promise of even more to come. With the introduction of flash controllers with support for the PCIe (PCI Express) interface and isolated uses of the technology on products like Apple&#8217;s latest MacBook Pros, the door has opened to questions about PCIe&#8217;s adoption and the benefits it poses to solid state storage. Below is a Q&amp;A with Jeremy Werner, Senior Director of Product and Customer Management at LSI\u2019s SandForce division.<\/p>\n<p>Q: Most client-based SSDs have used SATA in the past, while PCIe was mainly used for enterprise applications. Why is the PCIe interface becoming so popular for the client market?<\/p>\n<p>Jeremy: Over the past few decades, the performance of host interfaces for client devices has steadily climbed. Parallel ATA (PATA) interface speed grew from 33MB\/s to 100MB\/s, while the performance of the Serial ATA (SATA) connection rose from 1.5Gb\/s to 6Gb\/s. Today, some solid state drives (SSDs) use the PCIe Gen2 x4 (second-generation speeds with four data communication lanes) interface, supporting up to 20Gb\/s (in each direction). Because the PCIe interface can simultaneously read and write (full duplex) and SATA can only read or write at one time (half-duplex), PCIe can potentially double the 20Gb\/s speeds in a mixed (read and write) workload, making it nearly seven times faster than SATA.<\/p>\n<p>Will the PCIe interface replace SATA for SSDs?<\/p>\n<p>Jeremy: Eventually the replacement is likely, but it will probably take many years in the single-drive client PC market given two hindrances. First, some single-drive client platforms must use a common HDD and SSD connection to give users the choice between the two devices. And because the 6Gb\/s SATA interface delivers much higher speeds than than hard disk drives, there is no immediate need for HDDs to move to the faster PCIe connection, leaving SATA as the sole interface for the client market. And, secondly, the older personal computers already in consumers\u2019 homes that need an SSD upgrade support only SATA storage devices, so there\u2019s no opportunity for PCIe in that upgrade market.<\/p>\n<p>By contrast, the enterprise storage market, and even some higher-end client systems, will migrate quickly to PCIe since they will see significant speed increases and can more easily integrate PCIe SSD solutions available now.<\/p>\n<p>It is noteworthy that some standards, like M.2 and SATA Express, have defined a single connector that supports SATA or PCIe devices. The recently announced LSI SF3700 is one example of an SSD controller that supports both of those interfaces on an M.2 board.<\/p>\n<p>What is meant by the terms \u201cx1, x2, x4, x16\u201d when referencing a particular PCIe interface?<\/p>\n<p>Jeremy: These numbers are the PCIe lane counts in the connection. Either the host (computer) or the device (SSD) could limit the number of lanes used. The theoretical maximum speed of the connection (not including protocol overhead) is the number of lanes multiplied by the speed of each lane.<\/p>\n<p>What is protocol overhead?<\/p>\n<p>Jeremy: PCIe, like many bus interfaces, uses a transfer encoding scheme \u2013 a set number of data bits represented by a slightly larger number of bits called a symbol. The additional bits in the symbol constitute the inefficient overhead of metadata required to manage the transmitted user data. PCIe Gen3 features a more efficient data transfer encoding with 128b\/132b (3% overhead) instead of the 8b\/10b (20% overhead) of PCIe Gen2, increasing data transfer speeds by up to 21%.<\/p>\n<p>What is defined in the PCIe 2.0 and 3.0 specifications, and do end users really care?<\/p>\n<p>Jeremy: Although each PCIe Gen3 lane is faster than PCIe Gen2 (8Gb\/s vs 5Gb\/s, respectively), lanes can be combined to boost performance in both versions. The changes most relevant to consumers pertain to higher speeds. For example, today consumer SSDs top out at 150K random read IOPS at 4KB data transfer sizes. That translates to about 600MB\/s, which is insufficient to saturate a PCIe Gen2 x2 link, so consumers would see little benefit from a PCIe Gen3 solution over PCIe Gen2. The maximum performance of PCIe Gen2 x4 and PCIe Gen3 x2 devices is almost identical because of the different transfer encoding schemes mentioned previously.<\/p>\n<p>Full Story: <a href=\"http:\/\/www.techspot.com\/news\/56014-understanding-the-pcie-interface-and-how-it-benefits-solid-state-storage.html\" target=\"_blank\">Understanding the PCIe interface and how it benefits solid state storage &#8211; TechSpot<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Ever since solid state storage was put on the map, we&#8217;ve seen tremendous strides in storage performance across consumer and [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_feature_clip_id":0,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2},"jetpack_post_was_ever_published":false},"categories":[3,10],"tags":[812,933,1019],"class_list":["post-5077","post","type-post","status-publish","format-standard","hentry","category-hardware","category-technology","tag-pcie","tag-sata","tag-ssd"],"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/papNkV-1jT","jetpack-related-posts":[{"id":3177,"url":"https:\/\/nccomputertech.com\/techtalk\/2013\/08\/14\/sata-3-2-finalized-includes-sata-express-for-2-gbs-of-bandwidth\/","url_meta":{"origin":5077,"position":0},"title":"SATA 3.2 finalized, includes SATA Express for 2 GB\/s of bandwidth","author":"NCCT","date":"August 14, 2013","format":false,"excerpt":"SATA-IO, the group in charge of maintaining the SATA specification, has announced (PDF) that revision 3.2 of SATA has been finalized. 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